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2. SPARC, which one ?

This document deals only with SPARC based computers, in order to check, just type uname -m command and you should read something like sparc4x where x is blank,c,d,m,u if the system runs Solaris, or sparc for 32 bits SPARC architectures and sparc64 for 64 bits SPARC architectures if it runs Linux. 2.x.y

SPARC stands for Scalable Processor ARChitecture, it derives from research done between 1984-1988 on the RISC architecture at UC Berkeley. It exists 3 versions of this archiecture, SPARC-V7, SPARC-V8 (32 bits) and SPARC-V9 (64 bits). As you are likely to encounter a lot of implementations of the SPARC architecture, in the next section, the main features of theses processors are summarized.

2.1 Sun SPARC

This is quite obsolete, it is an implementation of the SPARC-V7 ; its main feature are an Integer unit (IU), an external Floating Point Unit (FPU), an unified data + instruction 64KB direct associative cache, and an Memory Managment Unit (MMU). There is a 4 stage pipeline for the integer instructions (fetch F, decode D, exec E, update WB) FPU and IU are synchronized.

2.2 Super SPARC

This is Texas Instrument and Sun's brainchild, it is usualy found at around 50Mhz clok rates featuring up to 1MB of L2 cache, it is available both as single and dual processor modules (SparcStation 10 and SparcStation 20). The higher clock frequency I have encountered so far is 60Mhz.

On a technical point of view this is a SPARC-V8 implementation, it is a superscalar processor, having 2 caches, one for instruction the other one for data.

  • The 20kB instruction cache is a 5 way associative.
  • The 16KB data cache is 4 way associative.

2.3 Micro SPARC

This is once again Texas Instrument and Sun's brainchild, it can be found in the SparcStation Classic, SparcStation LX, at frequency up to 50Mhz. Its derivative, the Micro SPARC II can be found in the SparcStation 4 and SparcStation 5 at frequencies up to 110Mhz.

On a technical point of view, its main features are a high level of integration, having 2 caches, one for instructions, the other one for data.

  • A 4KB instruction direct associative cache.
  • A 2KB data direct associative cache.

It is not possible to add an L2 cache. If you wish to learn more about the MicroSPARC processor you can browse Sun's Ultra SPARC ressources.

2.4 Hyper SPARC

This processor was introduced by ROSS in 1993, it is usualy found in the SparcStation 10, and SparcStation 20, at frequencies up to 150Mhz (I have heard of 200Mhz dual processor modules, but Have not witnessed one yet). It can be found on single or dual processor modules.

On a technical point of view it is an implementation of the SPARC-V8, it is superscalar. It can be found with L2 cache up to 512KB

2.5 ERC32

This is a radhard SPARC V7 microprocessor designed to be used on the space segment.

It comes as a single unit or as a three chip package. Main manufacturer is ATMEL in Nantes, France. At least, one software vendor claims to have GNU/Linux running on this CPU, this is for the This project has not been updated since March 2001. As I have not had the opportunity to check this claim. I am more than doubtful.

2.6 LEON

This is also a radhard implementation of the SPARC V8 designed to be used on the space segment. It is the ESA's brainchild and the lead designer is jiri gaisler. More information can be found on LEON's website:

The 2.4 and 2.5 kernel series are not yet supported, however the 2.0 kernel series is supported by the uClinux MMU less GNU/Linux distribution. This distribution has been built at ESA/ESTEC December 26 2003 on a SuSE 8.0 GNU/Linux distribution with gcc version 2.95.3 20010315 and a 2.4.18 kernel. Hereafter is the boot sequence and a sample session inside the tsim-leon simulator.

piou@linux:~/uClinux-dist/images> ./tsim-leon -nfp image.elf

 TSIM/LEON SPARC simulator, version 1.1.4a (evaluation version)

 Copyright (C) 2001, Gaisler Research - all rights reserved.
 This software may only be used with a valid license.
 For latest updates, go to
 Comments or bug-reports to

FPU disabled
serial port A on stdin/stdout
allocated 4096 K RAM memory, in 1 bank(s)
allocated 2048 K ROM memory
icache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
dcache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
section: .text at 0x0, size 252944 bytes
section: .data at 0x40000000, size 38452 bytes
section: .romfs at 0x3dc10, size 67584 bytes
tsim> g
resuming at 0x00000000
aCDG512k RAM

Found my key

Moved .data

Found my key

Flat model support (C) 1998-2000 Kenneth Albanowski, D. Jeff Dionne
LEON-2.1 Sparc V8 support (C) 2000 D. Jeff Dionne, Lineo Inc.
LEON-2.2/LEON-2.3 Sparc V8 support (C) 2001 The LEOX team <>.
Calibrating delay loop.. ok - 6.68 BogoMIPS
Memory available: 3904k/4080k RAM, 0k/0k ROM (176k kernel data, 247k code)
Swansea University Computer Society NET3.035 for Linux 2.0
NET3: Unix domain sockets 0.13 for Linux NET3.035.
uClinux version 2.0.39.uc2 (root@linux) (gcc version 2.95.3 20010315 (release)) 6 Thu Dec 26 18:28:01 PST 2002
LEON serial driver version 0.9
ttyS0 (irq = 3) is a builtin LEON UART
Blkmem copyright 1998,1999 D. Jeff Dionne
Blkmem copyright 1998 Kenneth Albanowski
Blkmem 1 disk images:
0: 3DC10-4E40F (RO)
VFS: Mounted root (romfs filesystem) readonly.

Sash command shell (version 1.1.1)
/> pwd
/> cd bin
/bin> pwd
/bin> ls

2.7 Ultra SPARC

The Ultra SPARC processor is an extension of the SPARC-V9 architecture, it is a 64 bits processor, it features some video processing instructions. It is found in all the computer whose name start with Ultra.

The Ultra SPARC II is an improvement of the Ultra SPARC, the Ultra SPARCIII is actually the second generation of Ultra SPARC processors, it was first introduced in the SunBlade 1000 Workstation. If wish to learn more about the UltraSPARC processors you can browse Sun's Ultra SPARC ressources.

2.8 SPARC64 V

This processor is based on the SPARC V9 and is made by Fujitsu It is a 64bits CPU with some very interesting error handling features such as ECC memory for the L1 cache, hardware instruction retry, error classification.

There is a 64 bit virtual address space and 43 bit physical address space. It is used in the PRIMEPOWER high end servers to mainframe class of Fujitsu's offering.

The cache is organized as :

  • A 128kB 2 way associative L1 instruction cache
  • A 128kB 2 way associative L1 data cache
  • A 2MB unified 4 way associative L2 cache

More information can be found on the whitepaper.

You may read the CPU-Design-HOWTO, this HOWTO has a lot of interesting links when it comes to studying the CPUs.

To summarize, the 32 bits workstations are the:

  • The sun4 workstation is the sun4/330 model.
  • The sun4c workstations are the SparcStation 1,2, IPC and IPX models.
  • The sun4m workstations are the SparcStation 5, 10 and 20.
Only the SparcStation 10 and SparcStation 20 are SMP capable: up to 2 CPU modules.

For more information on the SparcStation 5, 10, 20 you can read Sun's documentation online or download it available.

The following model have an 64 bits UltraSPARC architecture (sun4u). SunUltra 1, 2, 5, 10, 30, 60, 80 and SunBlade 1000, 1500, 2000. The SunUltra 2, 60, 80 and SunBlade 1000 are SMP capable, with the Ultra 80 and SunBlade 1000 and 2000 accepting up to 4 CPU modules, the SunUltra 2 and 60 accepting only 2 CPU modules.

The SunBlade 2000 is the latest one featuring Sun's latest marvel the Ultra III CPU, at a premium price of course. You can have a summary of the UltraWorkstation still in production at Sun's website.

A lot of information has been compiled in the Sun hardware reference that is found on many sites, or on SunHelp 's website.

2.9 Deciphering the CPUs

At first, a reference like SM61 or RT-200-D-125/512 seems to be, to say the least, quite cryptic. Actually, understanding theses references is really easy.

Ross Technology.

Theses CPUs's naming scheme is RT-a00-b-freq/cache where

  • a is a digit:
    • 1 SparcStation 10.
    • 2 SparcStation 20.
    • 6 SPARC MP600 ( not exactly a workstation ).
  • b is a letter:
    • D Dual CPU.
    • Q Quad CPU.
    • S Single CPU.
  • freq The frequency expressed in Megahertz.
  • cache The amount of cache memory expressed in Kilobytes.

When these modules are in a workstation the naming convention is HSxy, for example ywing is a SparcStation 20 HS22, thus it is easier to have a look inside the workstation.

SM modules.

This table is extracted from the FAQABOSS

Name  Speed( MHz )  Cache( MB ) Number of    SuperSparc 
                                 Processors   Series

SM20       33            0            1          I
SM30       36            0            1          I
SM40       40            0            1          I
SM41       40            1            1          I
SM50       50            0            1          I
SM51       50            1            1          I
SM512      50            1            2          I
SM51-2     50            2            1          I
SM61       60            1            1          I
SM61-2     60            2            1          I
SM71       75            1            1          II
SM71-2     75            2            1          II
SM81       85            1            1          II
SM81-5     85            2            1          II

Warning: the SM100 is a RT-600-D-40


Cypress manufactured SPARC compliants processors; AFAIK their naming scheme is CYnnn.

As you can see, this is easy to understand.

2.10 The javastation.

This is a family of Network computers that used to be manufactured by Sun, there is a very good JavaStation-HOWTO about it.

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